Reversing the algorithm is done by reversing the principle steps of the algorithm: By applying the reverse double dabble algorithm a BCD number can be converted to binary. Parametric Verilog implementation of the double dabble binary to BCD converter, 18-bit example.
Parametric Verilog implementation of the double dabble binary to BCD converter Sixteen shifts have been performed, so the algorithm terminates.
Now eight shifts have been performed, so the algorithm terminates. If any digit is five or above, three is added to ensure the value "carries" in base 10. Shifting left accomplishes both tasks simultaneously. The increment ensures that a value of 5, incremented and left-shifted, becomes 16 (10000), thus correctly "carrying" into the next BCD digit.Įssentially, the algorithm operates by doubling the BCD value on the left each iteration and adding either one or zero according to the original bit pattern. On each iteration, any BCD digit which is at least 5 (0101 in binary) is incremented by 3 (0011) then the entire scratch space is left-shifted one bit. The scratch space is initialized to all zeros, and then the value to be converted is copied into the "original register" space on the right. The diagram above shows the binary representation of 243 10 in the original register, and the BCD representation of 243 on the left. For example, if the original number to be converted is eight bits wide, the scratch space would be partitioned as follows: Then partition the scratch space into BCD digits (on the left) and the original register (on the right). It takes a maximum of 4 bits in binary to store each decimal digit. Reserve a scratch space wide enough to hold both the original number and its BCD representation n + 4× ceil( n/3) bits will be enough. Suppose the original number to be converted is stored in a register that is n bits wide.
0 kommentar(er)
